Freescale Semiconductor /MK60DZ10 /SIM /SCGC5

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SCGC5

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (0)LPTIMER 0 (0)REGFILE 0 (0)TSI 0 (0)PORTA 0 (0)PORTB 0 (0)PORTC 0 (0)PORTD 0 (0)PORTE

PORTE=0, PORTB=0, PORTC=0, PORTA=0, LPTIMER=0, REGFILE=0, PORTD=0, TSI=0

Description

System Clock Gating Control Register 5

Fields

LPTIMER

Low Power Timer Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

REGFILE

Register File Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

TSI

TSI Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTA

Port A Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTB

Port B Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTC

Port C Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTD

Port D Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

PORTE

Port E Clock Gate Control

0 (0): Clock disabled

1 (1): Clock enabled

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